1. Field
The invention relates to integrated circuit decoupling capacitors.
2. Background
The operation of high power, high speed integrated circuits can be affected by the electrical noise generated by the instantaneous switching of the transistors located in the circuit. It is well known that the inductive noise of an integrated circuit can be reduced by connecting decoupling capacitors to the circuit. Decoupling capacitors placed on power grids with current surges are able to smooth out voltage variations with current supplied from the stored charge on the decoupling capacitor.
Typically, a decoupling capacitor is placed on the opposite side of the package from the chip. Unfortunately, this arrangement is costly to manufacture, and the long lead lines from the power-consuming circuit to the capacitor electrodes contribute to an unacceptably high inductance. Such off-chip decoupling capacitors, however, are not sufficient for very high speed microprocessor applications. Since the decoupling capacitors are located at a relatively long distance from the switching circuits, the voltage drop caused by the high inductance path makes the off-chip capacitors unusable with gigahertz switching circuits. The voltage drop across an inductor is equal to L di/dt, where L is inductance and di/dt represents the change in current through a circuit over a period of time. Implicit in the di/dt is a frequency term omega, so as frequency goes up, inductive voltage drop becomes a larger part of the equation for power distribution. At very low frequencies, the only contributing impedance is the resistive voltage drop equal to iR, which is independent of frequency. At very low frequencies, power distribution is dominated by resistance.
Efforts have been made to integrate decoupling capacitors as part of the gate dielectric processing step. A portion of the chip is used to deposit the gate dielectric for use at the decoupling capacitor. An advantage to this is that there are no additional processing steps involved with fabricating the decoupling capacitor while using the gate dielectric. The disadvantages include the decoupling capacitor takes up high-value real estate on the chip as the capacitors compete for valuable die area that could be used for building additional circuits. Also when the capacitor is made with the gate oxide designed for very high transistor performance, there is a great deal of leakage. Although it is possible to integrate chip capacitors within the chip's circuit elements, due to limited area in which to build these capacitors, the overall capacitive decoupling that they provide is also limited.
Another approach to decoupling capacitor fabrication is illustrated in
FIG. 1. FIG. 1 illustrates a decoupling capacitor that may be fabricated on top of a metal line in an integrated circuit. In one embodiment, the metal layer comprises Vcc 35 and Vss 30. On top of Vcc line 35 is a decoupling capacitor stack comprising lower electrode 18, capacitor material 16 of a generally high dielectric constant, and top electrode 14, the whole of which is passivated by a global layer of silicon nitride 20. Surrounding all metal lines in these metal layers is interlayer dielectric (ILD) 10 that is usually a Plasma Tetra Ethyl Ortho Silicate (PTEOS) oxide. FIG. 1 shows a Vss 30 coupled through an opening in passivation layer 20 through a decoupling capacitor stack 18, 16, and 14 to metal Vcc 35. This figure forms a decoupling capacitor between Vcc line 35 and Vss line 30. The advantages to this embodiment are that no additional real estate on the chip is taken up for fabrication of the decoupling capacitor, and the decoupling capacitor is no more than 70 microns from the integrated circuit element it is supporting. An off-chip decoupling capacitor is typically a millimeter in distance from the circuit element it is supporting.
A disadvantage of stacking the decoupling capacitors over the metal lines is illustrated in FIG. 2. Ideally, on chip decoupling capacitors are strapped off less than every 10 microns. However, due to structural limitations inherent in the layout of the chip and package bumps, the area of copper line 35, which in this example is a Vcc line, covered by the capacitor stack and particularly electrode 14 of the capacitor stack, can be much greater than metal contact 30 through the passivating layer to top electrode 14. In one embodiment, this long capacitor stack may create wings of top electrode that extend 75 microns from the strapping contact.
In one embodiment, both Vss contact 30 and Vcc metal line 35 are made of copper, a highly conductive material. Top capacitor electrode 14 may be made of, for example, tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN). These typical top electrode materials generally have a much higher resistivity than copper. In one embodiment, where the top electrode is tantalum nitride, the resistivity of the top electrode is typically about 250 micro-ohm per centimeter (μohm cm.). Copper typically has a resistivity of 2 μohm cm. This change in resistivity can lead to an RC time constant loss as distant areas of the capacitor stack, say for example at point B of FIG. 2, require longer time to charge and discharge than areas of the capacitor stack near a conductive material, say for example point A.
The distance between points A and B in the top electrode shown in FIG. 2 is the distance over which a current has to travel to extract the charge at point B. This distance is called the strapping distance, W. This distance can be, in some instances, as much as 75 microns. The capacitance built up at point B then has to travel to point A in the relatively high resistivity top electrode 14 to contribute its charge. A time constant τ, is equivalent to RC (resistance times capacitance) in a RC circuit. RC is a rough measure of the time it would take to charge a capacitor through the distance from a constant voltage supply. R in this circuit is proportional to the distance between point A and point B or W, as is C. Thus τ is proportional to the square of the strapping distance, W. In the embodiment where the strapping distance is increased from about 10 microns to about 75 microns, the time constant increases by the square of the increase in distance of 7.5 to about 56, this would roughly translate to a delay of 10 nanosecond (nsec) or a maximum response frequency of 100 MHz. This increase in the time constant necessitates a reduction in the frequency of operation the decoupling capacitors may support.